1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to power management of a portable computer system.
2. Description of Related Art
The conservation of power remains particularly important in portable electronic devices. Laptop and notebook computers are typically designed for use with batteries, away from power outlets. Most battery packs can only power a computer for a few hours of continuous use. Therefore, portable personal computers need to be designed for very low power operation in order to conserve the limited charge of the battery. For this same reason, portable personal computers should also be designed for maximum efficiency with respect to how power is drawn from the battery.
The battery normally supplies power to the microprocessor through a dc-to-dc converter. At very low currents, the power efficiency of the dc-to-dc converter is low. At very high currents, the power efficiency of both the battery and the dc-to-dc converter is low. Thus, for maximum power efficiency, power needs to be drawn from the battery at intermediate and moderate levels whenever there is a substantial queue of useful computation to be done.
Typically, portable computer systems provide a variety of mechanisms for minimizing the electrical current consumption during computer operation. For example, systems usually implement sleep modes and standby modes for input/output devices. The largest consumer of power in a portable computer is the display. One way the prior art has implemented power conservation is by disabling the power to the display when it is not in use.
Another consumer of power is the microprocessor and its motherboard. The microprocessors used in portable computers are derived from microprocessors designed originally for desktop computers, where power consumption was not as important. In the prior art, computer manufacturers have merely reduced the supply voltage and clock rate of a microprocessor to make it suitable for portable use. The frequency of the microprocessor clock determines the rate at which the processor fetches and executes instructions. Reducing this clock rate reduces the number of executable instructions (node toggles) processed and the corresponding current draw necessary to implement them.
In U.S. Pat. No. 5,630,143 issued to Maher, et al., on May 13, 1997, entitled "MICROPROCESSOR WITH EXTERNALLY CONTROLLABLE POWER MANAGEMENT", the microprocessor clock signals are disabled and enabled by a control signal. By suspending the clocks to the core circuitry and memory circuitry, a significant reduction in the power consumed by the microprocessor is realized. The operation of the microprocessor may also be suspended, responsive to a software command for devices that support a HALT command or similar executable function.
In U.S. Pat. No. 5,189,647 issued to Suzuki et al., on Feb. 23, 1993, entitled "INFORMATION PROCESSING SYSTEM HAVING POWER SAVING CONTROL OF THE PROCESSOR CLOCK", the frequency of the clock signal is reduced rather than having the clock to the processor completely stopped.
Similarly, in U.S. Pat. No. 5,630,148 issued to Norris on May 13, 1997, entitled, "DYNAMIC PROCESSOR PERFORMANCE AND POWER MANAGEMENT IN A COMPUTER SYSTEM", the processor executes a performance manager program that writes to a clock speed register according to a performance state selected by an application program. A performance state table, maintained by the performance manager program, stores a set of clock frequencies that correspond to a set of performance states for the processor. The application program selects the performance state to maximize performance during processor intensive functions and to maximize power conservation during interactive functions.
Another method of power conservation is to have the microprocessor system enter the power management mode by an optimal time out value, as taught in European Patent No. EP 0 750 248 A2, issued to Kawano, et al., on Jun. 6, 1996, entitled, "AN INFORMATION PROCESSING SYSTEM HAVING A POWER SAVING FUNCTION AND A CONTROL METHOD THEREFOR". In Kawano, power consumption is reduced in response to a timer indicating that a predetermined time has elapsed since the last operation. Once a time out has occurred, the system is arranged to change between its normal modes of operation and a power management mode. The personal computer system is then able to perform such power management operations as LCD-off (liquid crystal display off), HDD-off (hard disc drive off), and a Suspend/HALT operation.
Recent advances in microprocessor design have complicated the power problem for portable computers. Today, super pipeline processors have the ability to run many speculative operation codes (opcodes) in order to improve the overall performance of the processor. However, this speculative function can also adversely affect power consumption. If on the average, five to seven execute cycles are running, with an effective performance improvement of less than 50%, the ratio of executed functions versus power consumption will not be linear, i.e., multiple execution units operating consecutively will not correspond to a one-for-one increase in performance. This non-linear improvement in performance will consume considerably more power. Thus, at times, speculative execution may not be warranted.
If, however, one wants to dynamically manage the power consumption inside battery powered portable computers, some form of power management of execution or power consumption allocation is desirable. In particular, speculative execution units may be monitored and curtailed whenever the current drain on the battery is outside the range of maximum battery conversion efficiency. Additionally, by maintaining a constant load on the battery, battery life may be extended.
Power analysis tools currently exist to calculate the power consumption of an execution unit when its nodes toggle. The number of node toggles depends on the function being executed. The ability to control the dynamic execution of logic to conserve power is taught by the present invention. This allows power allocation to be based on current system needs and program execution.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to manage a balance between performance and power consumption in a computer system.
It is another object of the present invention to provide a portable, battery powered computer system with improved power conservation.
A further object of the invention is to increase battery life by maintaining a constant load on the battery during operation.
It is another object of the present invention to dynamically allocate power to the system logic circuitry.
Another object of the present invention is to monitor active execution units including determining an expected total power consumption value based on the measured power allocation attributed to each execution unit performed.
It is yet another object of the present invention to compare the expected total power consumption value to a power efficiency value associated with the optimum battery output.
A further object of the present invention is to cancel selected execution unit activities whenever the expected total power consumption value exceeds the power efficiency value.
Another object of the present invention is to add executable unit activities to sustain the expected total power consumption value within the range of maximum battery conversion efficiency.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.